First Meeting: How to make the translator

Checking the correctness of a Logisim circuit will consist of two major steps.

• Checking the syntactical correctness of the circuit (the various parts of the circuit and the connections in between)
• Checking the semantical correctness of the circuit (if the circuit is able to do the things it was supposed to do)

Syntactical Correctness

When we build a Logisim circuit, we notice that Logisim imposes some rules on the circuit. To verify the correctness of a solution, we will first execute 2 kinds of checks that will test the syntactical correctness of the Logisim input circuit.

• A Logical Check of the circuit: e.g. when clocked elements are present in the circuit, there needs to be a clock
• A Problem Specific Check: e.g. if the assignment states that there need to be 3 AND-gates, we need to check this

These restrictions will take the form of rules.

How will we verify this extra set of rules?

• First we export our circuit to xml format and load the tree-structure into memory.
• Then we travel down the tree and test it. We have to make sure that every test corresponds to a requirement.
• After the test a report will be generated, containing the test results.

Semantical Correctness

The next phase in ensuring correctness will be to check the semantics of the input circuit. For this purpose we will use the Verilog testbenches.

Since Verilog testbenches are obviously unable to test a Logisim circuit, the Logisim circuit first needs to be translated into Verilog. Therefore we will convert the Logisim tree structure into a tree structure more fit to represent a Verilog module. This tree structure will then be converted into Verilog code. When this is done, the testbenches will be allowed to run and a semantical report will be produced.

After The First Semester: What I've done up until now

The Intermediate Tree

In the first semester I worked on my intermediate tree for the AND, OR and NOT gates.

This tree is structured as followed:

• The root of the tree will be the main circuit
• Every component in the main circuit will be a child of the circuit (example: when an and gate is drawn in the main circuit, the and gate will be a child of the root).
• When the main circuit contains other circuits, that circuit will also be a child and the components that this child circuit has, will be children of the child circuit.

I also wrote a couple of tests, to see if my implementation really works.

How to deal with the wires?

The main problem with the wires: the angles. We need to translate these angles to straight lines:

In the logisim xml file, we will see (in the case of the image) 6lines. These six lines will be represented in the intermediate tree by three wires.

Class Diagrams

Program

Thesis