Yentl Van Tendeloo   
M. Sc. Student
Modelling, Simulation and Design Lab
Department of Mathematics and Computer Science
University of Antwerp
Middelheimcampus
1, Middelheimlaan
Antwerp,
Belgium 2020
e-mail:
www:
yentl.vantendeloo@student.ua.ac.be
http://msdl.cs.mcgill.ca/people/yentl
Yentl Van Tendeloo     
   

I am a first year master student at the University of Antwerp. This page is for my research internship, which is supervised by Prof. Hans Vangheluwe in MSDL (Modelling, Simulation and Design Lab).


Research Internship II: Distributed and parallel DEVS simulation

Read more on my research internship II here.


Research Internship I: Optimizing the PythonDEVS simulator

Read more on my research internship I here.


Model Driven Engineering project: Modelling the DEVS formalism, including symbolic flattening

All information about my MDE project can be found here.


Bachelor thesis: Logisim to DEVS translation

Read more on my bachelor project here.

My bachelor project is currently finished and can be found here:
Maintained by Yentl Van Tendeloo. Last Modified: 2011/09/07 08:19:52.